Logical Built-in Self Test of integrated circuits is well known and widely used in the art of production testing of integrated circuits (IC) in order to detect and isolate any faults in the IC. FIG. 1 is a block diagram of a typical LBIST system. A pseudo-random pattern generator (PRPG) generates a pseudo-random pattern of data that is coupled as inputs to a number of parallel scan chains 1 through “N”. Each chain is comprised of a series of latches. Test data is fed into the first latch in a chain on each scan chain clock cycle and on each scan chain clock cycle the data in the proceeding latch in the chain is shifted to the succeeding latch in the chain. This procedure continues until all of the latches in the chain are loaded with data. Once all of the latches have been loaded, a functional clock is applied to the circuit under test. In a typical LBIST system the outputs of the chains in response to the functional clock is coupled to a multiple input signature register (MISR), which compresses the data and provides a data signature that can be compared with a known good signature. Scan chains are also referred to in the art as STUMPS, which is an acronym for Self-Test Using MISR and Pseudo-random pattern generator. As used herein the connections from the PRPG to the MISR are referred to as stumps. The cells (e.g. Macros and Units) are referred to as chains and the latches reside inside of each of these chains.
FIG. 2 is a block diagram of a typical LBIST system for testing an IC with several hierarchical levels. In this illustrative example, a stump 1 path comprises LBIST type 1 chains included in Macro A, Macro B, and Unit A coupled in series; a stump 2 path comprises type 2 chains included in Macro A and Macro B coupled in series; and stump N comprises a type 2 chain in Unit A.
FIG. 3 is a block diagram similar to FIG. 2 in illustrating the fact that, in some test systems in use, the input to each stump in some systems is not generated by a PRPG and the output is not captured by a MISR.
The connections between the PRPG and the MISR have both logical and physical constraints. These connections, which make up hundreds or thousands of nets in an IC, can cause timing and routing issues. There are timing restrictions on the connections that go from the MISR/PRPG to the chains, between the chains, and from the chains to the MISR/PRPG.